The present invention relates generally to semiconductor processing technology, and more particularly to a method for manufacturing static random access memory (SRAM) devices with reduced threshold voltage deviation.
As semiconductor processing technology advances, integrated circuit (IC) devices continue to shrink in size. In order to reduce short channel effect, the thermal budget and source/drain dopant density are reduced as the size of IC device shrinks. Such low dopant density often causes a depletion region formed between a polysilicon gate layer and its underlying gate dielectric layer. In order to eliminate this depletion region, conventionally, a pre-gate doping step is performed to increase the gate dopant density after the polysilicon gate layer is deposited on the gate dielectric layer. The pre-gate doping is used extensively in manufacturing various IC devices, such as SRAM.
FIG. 1 schematically illustrates a typical SRAM cell 100, which comprises PMOS transistors 102 and 104, as well as NMOS transistors 106, 108, 110 and 112. PMOS transistor 102 and NMOS transistor 106 are serially coupled between a supply voltage Vcc and a device ground, which can be any voltage lower than Vcc. Similarly, PMOS transistor 104 and NMOS transistor 108 are coupled between the supply voltage Vcc and the device ground. The gates of PMOS transistor 102 and NMOS transistor 106 are tied together, and further connected to the drains of PMOS transistor 104 and NMOS transistor 108. Similarly, the gates of PMOS transistor 104 and NMOS transistor 108 are tied together, and further connected to the drains of PMOS transistor 102 and NMOS transistor 106. NMOS transistor 110 is coupled between a node 114 and a bit line BL, whereas NMOS transistor 112 is coupled between a node 116 and a complementary bit line BLB. NMOS transistors 110 and 112 function as pass gate switches that selectively allows the cell 100 to be accessed for read or write operation.
One drawback of the conventional pre-gate doping applied to an SRAM device is that inter-gate diffusion may occur to cause a wide variation of threshold voltages among its memory cells. FIG. 2 illustrates a layout view of the SRAM cell 100 on a substrate and poly silicon level. An area 202 defined by broken lines represents where PMOS transistors 102 and 104 are constructed. The areas outside the area 202 represent where NMOS transistors are constructed. As shown in the drawing, a polysilicon layer 204 extending across the area 202 forms the polysilicon gate layer for both PMOS transistor 102 and NMOS transistor 106, wherein the portion inside the area 202 is doped with P-type impurities and the portion outside the area 202 is doped with N-type impurities in the pre-gate doping process. During a subsequent annealing process, the P-type impurities would diffuse toward the N-type impurities, and vice versa, thereby resulting in a wide variation of threshold voltage among the SRAM cells.
FIG. 3 illustrates a chart showing the sensitivity of the threshold voltage variation to a distance marked by label “A” between an N+ implant region of NMOS transistor 106 and an oxide defined area of PMOS transistor 102. The x-axis of the chart represents the distance in units of nm, and the y-axis represents the threshold voltage variation in units of percentage. As shown in the chart, as the distance “A” decreases the variation of threshold voltage increases. Given that the SRAM devices continuously shrink in size as semiconductor processing technology advances, the problem of threshold voltage variation becomes increasingly serious.
As such, what is needed is a method for manufacturing SRAM devices with reduced threshold voltage deviation.